High-level digital design methodology using VHDL/Verilog, Design, Implementation, and Verification, Application requiring HW implementation, Floating-Point to Fixed-Point Conversion, Architectures for Basic Building Blocks, Adder, Compression Trees, and Multipliers, Transformation for high speed using pipelining, retiming, and parallel processing, Dedicated Fully Parallel Architecture, Time shared Architecture, Hardwired State Machine based Design, Micro Program State Machine based Design, FPGA-based design and logic synthesis.

This Course Will Map to PLO-1, PLO-2 and PLO-3, PLO-9 and PLO-10